A semiconductor device, for example, a dynamic random access memory (DRAM), stores data that is used by a device of a system. A double data rate (DDR) memory, which is a semiconductor device, receives and outputs data on both the rising and falling edges of a clock signal or a strobe signal. The DDR memory increases the operation speed of the system.
The device of the system provides commands to the memory, and the memory is operated in accordance with the commands. For example, the device provides a read command and a read address to the memory. The memory reads data corresponding to the read address from cell arrays based on the read command. The memory generates a data strobe signal and outputs the read data in synchronization with the data strobe signal. The device in the system includes a reception circuit that receives the data strobe signal and the read data from the memory. The reception circuit adjusts the timing of the data strobe signal and retrieves the read data in accordance with the data strobe signal.
Relative timing (phase) differences between the read data and the data strobe signal may cause errors in the read data. Thus, the device includes a circuit that adjusts the timing of the data strobe signal relative to the read data. Japanese Laid-Open Patent Publication Nos. 2012-27734, 2012-58997, and 2013-58209 describe a circuit that adjusts the timing of the data strobe signal.
In the system, the device includes a core circuit (e.g., CPU), which controls the input and output of data between the device and the memory, and a control circuit (i.e., memory controller (MC)), which controls the memory. The core circuit and the control circuit receive and output data in accordance with an internal clock signal (e.g., system clock signal) that is used to operate the device in the system. After receiving the read data in accordance with the data strobe signal, the reception circuit outputs the read data in accordance with the internal clock signal.
Relative timing differences between the internal clock signal and the data strobe signal occur due to various factors including variations in operation voltage of the device and temperature change (referred to as VT drift). Such timing differences between the internal clock signal and the data strobe signal may cause an error in the read data that is output from the reception circuit in accordance with the internal clock signal.